The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Aug. 26, 2014
Applicants:

James C. Holt, Austin, TX (US);

Brian C. Kahne, Austin, TX (US);

William C. Moyer, Dripping Springs, TX (US);

Inventors:

James C. Holt, Austin, TX (US);

Brian C. Kahne, Austin, TX (US);

William C. Moyer, Dripping Springs, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/32 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/321 (2013.01); G06F 9/3869 (2013.01); G06F 9/461 (2013.01); G06F 9/50 (2013.01);
Abstract

A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.


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