The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jul. 05, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Takao Toi, Kanagawa, JP;

Taro Fujii, Kanagawa, JP;

Yoshinosuke Kato, Kanagawa, JP;

Toshiro Kitaoka, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 9/44 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 17/50 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3887 (2013.01); G06F 17/505 (2013.01); G06F 17/5054 (2013.01); G06F 15/7867 (2013.01); Y02B 60/1207 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A parallel arithmetic device includes a status management section, a plurality of processor elements, and a plurality of switch elements for determining the relation of coupling of each of the processor elements. Each of the processor elements includes an instruction memory for memorizing a plurality of operation instructions corresponding respectively to a plurality of contexts so that an operation instruction corresponding to the context selected by the status management section is read out, and a plurality of arithmetic units for performing arithmetic processes in parallel on a plurality of sets of input data in a manner compliant with the operation instruction read out from the instruction memory.


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