The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Apr. 08, 2015
Applicant:

Luxvue Technology Corporation, Santa Clara, CA (US);

Inventors:

Dariusz Golda, Redwood City, CA (US);

Andreas Bibl, Los Altos, CA (US);

Assignee:

LuxVue Technology Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/266 (2006.01); H05K 1/02 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 21/683 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0284 (2013.01); H01L 21/6833 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H05K 1/03 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H05K 2201/09036 (2013.01);
Abstract

A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure.


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