The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2016
Filed:
Oct. 30, 2012
Applicant:
Verisiti, Inc., Sanford, NC (US);
Inventor:
William Eli Thacker, Sanford, NC (US);
Assignee:
Verisiti, Inc., Sanford, NC (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); H01L 21/82 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H03K 19/20 (2013.01); H01L 21/82 (2013.01); H01L 23/573 (2013.01); H01L 27/0203 (2013.01); H01L 27/06 (2013.01); H01L 28/24 (2013.01); H01L 2924/0002 (2013.01);
Abstract
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.