The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2016
Filed:
May. 23, 2012
Applicants:
Toru Nakura, Tokyo, JP;
Kunihiro Asada, Tokyo, JP;
Inventors:
Toru Nakura, Tokyo, JP;
Kunihiro Asada, Tokyo, JP;
Assignee:
AIKA DESIGN INC., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03K 3/01 (2006.01); H03L 7/099 (2006.01); H03K 5/153 (2006.01); G04F 10/00 (2006.01); H03L 7/07 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
H03K 3/01 (2013.01); G04F 10/005 (2013.01); H03K 5/153 (2013.01); H03L 7/07 (2013.01); H03L 7/089 (2013.01); H03L 7/0812 (2013.01); H03L 7/0816 (2013.01); H03L 7/099 (2013.01);
Abstract
A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTCgenerates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.