The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Jul. 06, 2012
Applicants:

Tatsuya Sugimachi, Tokyo, JP;

Satoshi Torii, Tokyo, JP;

Inventors:

Tatsuya Sugimachi, Tokyo, JP;

Satoshi Torii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 21/8234 (2006.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/0433 (2013.01); H01L 21/823468 (2013.01); H01L 27/11524 (2013.01); H01L 29/6656 (2013.01);
Abstract

A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.


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