The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Jun. 08, 2015
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Lars-Ake Ragnarsson, Leuven, BE;

Tom Schram, Rixensart, BE;

Hendrik F. W. Dekkers, Tienen, BE;

Soon Aik Chew, Leuven, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 27/112 (2013.01);
Abstract

The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.


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