The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Apr. 27, 2015
Applicant:

Sanmina Corporation, San Jose, CA (US);

Inventor:

Paul Sweere, San Clemente, CA (US);

Assignee:

Sanmina Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B23K 31/02 (2006.01); H01L 23/00 (2006.01); H05K 3/46 (2006.01); B23K 1/00 (2006.01); H05K 1/14 (2006.01); H05K 3/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H05K 3/34 (2006.01); H01L 25/03 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); B23K 1/0016 (2013.01); B23K 31/02 (2013.01); H01L 23/49816 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H05K 1/141 (2013.01); H05K 3/0052 (2013.01); H05K 3/4697 (2013.01); B23K 2201/42 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/03 (2013.01); H01L 2224/11822 (2013.01); H01L 2224/131 (2013.01); H01L 2224/133 (2013.01); H01L 2224/13294 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/8192 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81205 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/93 (2013.01); H01L 2924/1436 (2013.01); H05K 1/144 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10378 (2013.01); Y10T 29/49165 (2015.01);
Abstract

Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).


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