The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Apr. 16, 2012
Applicants:

Katsuhiko Yanagawa, Hino, JP;

Yoshinari Ikeda, Matsumoto, JP;

Inventors:

Katsuhiko Yanagawa, Hino, JP;

Yoshinari Ikeda, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/08 (2006.01); H01L 25/07 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01); H01L 25/18 (2006.01); H01L 21/56 (2006.01); H01L 25/16 (2006.01); H01L 23/053 (2006.01);
U.S. Cl.
CPC ...
H01L 23/08 (2013.01); H01L 21/565 (2013.01); H01L 23/29 (2013.01); H01L 23/3135 (2013.01); H01L 25/07 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 21/561 (2013.01); H01L 23/053 (2013.01); H01L 25/162 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A power semiconductor module has an insulating layer; a copper base substrate having first and second copper blocks, either the first or the second copper block being fixed on one side and the other being fixed on the other side of the insulating layer; a plurality of power semiconductor elements using silicon carbide, and having one side fixed onto the first copper block with a conductive bond layer; a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a conductive bond layer; a printed circuit board fixed to the implant pins and disposed to face the power semiconductor elements; a first sealing material containing no flame retardant, and disposed at least between the power semiconductor elements and the printed circuit board; and a second sealing material containing a flame retardant, and disposed to cover the first sealing material.


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