The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Nov. 07, 2012
Applicants:

Su-a Kim, Seongnam-si, KR;

Young-soo Sohn, Seoul, KR;

Dae-hyun Kim, Hwaseong-si, KR;

Inventors:

Su-a Kim, Seongnam-si, KR;

Young-soo Sohn, Seoul, KR;

Dae-hyun Kim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/20 (2006.01); G06F 12/00 (2006.01); G11C 29/04 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/04 (2013.01); G11C 29/808 (2013.01); G11C 29/81 (2013.01); G11C 29/848 (2013.01); G11C 7/1045 (2013.01);
Abstract

In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.


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