Dynamic write port re-arbitration

Abstract

Within a processing pipelineissue control circuitryserves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipelineIf not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stagePartway along the processing pipelinestate becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitryserves to bypass the denormal handling pipeline stagesuch that the output operand will be written to the register bankone processing cycle earlier. Write port usage is tracked by a write port usage scoreboardwhich is both read and updated by the bypass circuitrywhen re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline