The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Mar. 14, 2014
Applicant:

Saankhya Labs Private Limited, Bangalore, IN;

Inventors:
Assignee:

Other;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01); G06F 11/10 (2006.01); H04L 1/00 (2006.01); H03M 13/27 (2006.01);
U.S. Cl.
CPC ...
H03M 13/11 (2013.01); G06F 11/10 (2013.01); H03M 13/114 (2013.01); H03M 13/1137 (2013.01); H03M 13/1165 (2013.01); H03M 13/1168 (2013.01); H03M 13/6505 (2013.01); H03M 13/6519 (2013.01); H03M 13/27 (2013.01); H04L 1/0041 (2013.01); H04L 1/0045 (2013.01); H04L 1/0057 (2013.01);
Abstract

A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.


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