The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

May. 23, 2014
Applicants:

Ja-young Lee, Hwaseong-si, KR;

Se-myeong Jang, Anyang-si, KR;

Inventors:

Ja-Young Lee, Hwaseong-si, KR;

Se-myeong Jang, Anyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 27/108 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76229 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/11531 (2013.01);
Abstract

According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.


Find Patent Forward Citations

Loading…