The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Mar. 10, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

William Tyler Weaver, Austin, TX (US);

Malcolm N. Daniel, Jr., Austin, TX (US);

Robert B. Vopat, Austin, TX (US);

Jason M. Schaller, Austin, TX (US);

Jacob Newman, Palo Alto, CA (US);

Dinesh Kanawade, Sunnyvale, CA (US);

Andrew J. Constant, Cupertino, CA (US);

Stephen C. Hickerson, Hollister, CA (US);

Jeffrey C. Hudgens, San Francisco, CA (US);

Marvin L. Freeman, Round Rock, TX (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67196 (2013.01); H01L 21/67742 (2013.01);
Abstract

A wafer handling system may include upper and lower linked robot arms that may move a wafer along a nonlinear trajectory between chambers of a semiconductor processing system. These features may result in a smaller footprint in which the semiconductor processing system may operate, smaller transfer chambers, smaller openings in process chambers, and smaller slit valves, while maintaining high wafer throughput. In some embodiments, simultaneous fast wafer swaps between two separate chambers, such as load locks and ALD (atomic layer deposition) carousels, may be provided. Methods of wafer handling are also provided, as are other aspects.


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