The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Jun. 30, 2015
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Kazuhisa Torigoe, Tokyo, JP;

Toshiaki Ono, Tokyo, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/322 (2006.01); H01L 21/02 (2006.01); C30B 25/10 (2006.01); H01L 21/20 (2006.01); C30B 25/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3221 (2013.01); C30B 25/10 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); C30B 25/02 (2013.01); H01L 21/20 (2013.01); H01L 21/3225 (2013.01);
Abstract

A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film-growth step in which an epitaxial film is grown on a silicon wafer in a reaction container, and a temperature reduction step in which a temperature of the epitaxial silicon wafer is reduced from a temperature at which the epitaxial film is grown. In the temperature reduction step, a temperature reduction rate of the epitaxial silicon wafer is controlled to satisfy a relationship represented by R≦2.0×10-4X, where X (Ω·cm) represents a resistivity of the silicon wafer, and R (degrees C./min) represents the temperature reduction rate for lowing the temperature of the epitaxial silicon wafer from 500 degrees C. to 400 degrees C.


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