The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2016
Filed:
Mar. 05, 2014
Applicant:
Huawei Technologies Co., Ltd., Shenzhen, Guangdong, CN;
Inventors:
Rami Zecharia, Munich, DE;
Yaron Shachar, Munich, DE;
Assignee:
Huawei Technologies Co., Ltd., Shenzhen, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/413 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); H04L 12/933 (2013.01); H04L 12/861 (2013.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/413 (2013.01); G06F 12/023 (2013.01); G06F 13/1684 (2013.01); H04L 49/10 (2013.01); H04L 49/90 (2013.01); G06F 12/06 (2013.01); G06F 2212/2532 (2013.01);
Abstract
A memory system () comprising a control logic () adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (), wherein n is a natural number; and n+1 memory banks () of a shared memory () adapted to store data, wherein the control logic () is adapted to control a memory bank occupancy level MBOL of each memory bank () such that the differences between memory bank occupancy levels MBOLs of the memory banks () are minimized.