The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Dec. 16, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Darren L. Anand, Williston, VT (US);

Venkatraghavan Bringivijayaraghavan, Cheyyar, IN;

Krishnan S. Rengarajan, Bangalore, IN;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/406 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/406 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/40618 (2013.01);
Abstract

A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.


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