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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9280737 B1

PDFFull Text
Date of Patent:
Mar. 08, 2016

Filed:

Aug. 20, 2014

System in package structure, electroplating module thereof and memory storage device

Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Chun-Feng Lee, Hsinchu, TW;

Chien-Liang Chang, Hsinchu County, TW;

Hsuan-Teng Cheng, Kaohsiung, TW;

Assignee:

PHISON ELECTRONICS CORP., Miaoli, TW;

Attorney:

Jianq Chyun IP Office

Primary Examiner:

Stephen W Smoot

Int. Cl.
CPC ...
H01L 23/49 (2006.01); G06K 19/077 (2006.01); G11C 16/04 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); C25D 17/00 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06K 19/07732 (2013.01); C25D 17/007 (2013.01); G06K 19/07722 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 16/04 (2013.01); H01L 23/49 (2013.01); H01L 23/49811 (2013.01); H01L 23/5223 (2013.01); H01L 25/0655 (2013.01);
Abstract

A system in package (SIP) structure, an electroplating module thereof and a memory storage device are provided. The SIP structure includes a first layout layer, a second layout layer and a rewritable non-volatile memory module. The first layout layer includes a first pad and a wire. The first pad is close to a first side of the first layout layer, and the first pad is configured to couple to a ground voltage. One terminal of the wire is coupled to the first pad, and another terminal of the wire is coupled to an opening of the SIP structure, wherein the opening is located at a second side of the first layout layer opposite to the first side, and the opening is configured to couple to an external voltage.

Find Patent Forward Citations

Lee, Chun-Feng. (2016). System in package structure, electroplating module thereof and memory storage device (U.S. Patent No. 9280737). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9280737

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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