The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

May. 18, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventor:

Dov Levenglick, Givat Ada, IL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/145 (2013.01); G06F 12/1009 (2013.01); G06F 12/1036 (2013.01); G06F 12/1072 (2013.01); G06F 12/1491 (2013.01); G06F 12/109 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/151 (2013.01); G06F 2212/657 (2013.01);
Abstract

A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. A memory management unit determines whether a write access to the first storage location is allowable. The access is to store memory mapping information relating to a first actual physical address. The memory management unit prevents the write access if the first actual physical address is not in the allowed address range, and does not prevent the write access if the first actual physical address is in the allowed address range. The memory management unit prevents a write access to the second storage location by a process that is not running in a hypervisor mode.


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