The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

May. 22, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Qunying Li, Allen, TX (US);

Joao Carlos Brito, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/78 (2006.01); H03M 1/80 (2006.01); H03M 1/68 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1057 (2013.01); H03M 1/687 (2013.01); H03M 1/785 (2013.01); H03M 1/808 (2013.01);
Abstract

One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/−0.5 LSB).


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