The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Dec. 24, 2014
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsien, TW;

Inventors:

Po-Nien Lin, Zhubei, TW;

Jiunn-Yih Lee, Zhubei, TW;

Assignee:

MStar Semiconductor, Inc., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/10 (2006.01); H03L 7/085 (2006.01); G09G 5/00 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); G09G 5/008 (2013.01); H04L 7/033 (2013.01); H04L 7/0004 (2013.01); H04L 7/0008 (2013.01);
Abstract

A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.


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