The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9276040 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 01, 2016

Filed:

Jan. 16, 2015
Applicants:

Board of Regents of the University of Nebraska, Lincoln, NE (US);

The Board of Regents of the University of Texas System, Austin, TX (US);

The Research Foundation for the State University of New York Stor—university AT Buffalo, Amherst, NY (US);

Inventors:

Andrew Marshall, Richardson, TX (US);

Peter A. Dowben, Crete, NE (US);

Jonathan P. Bird, Buffalo, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H01L 29/82 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H03K 19/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H03K 19/16 (2013.01);
Abstract

Majority and minority logic can be implemented by voltage controlled switching of magneto-electric layers of magneto electric magnetic tunnel junction (ME-MTJ) devices. A ME-MTJ device includes an exchange bias-controlled switching element and a pinned ferromagnetic layer on an antiferromagnetic layer. In one case, the switching element includes a magneto electric (ME) layer on a free ferromagnetic (FM) layer, and is separated from the pinned FM layer by an insulator. To implement a majority or minority logic gate a single ME-MTJ device may be used where the device is provided with three electrodes contacting the ME layer in an overlaying relationship with the ME layer. The orientation of the pinned FM layer indicates whether the gate is a majority or a minority logic gate.


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