The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Mar. 18, 2015
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Jon D. Cheek, Cedar Park, TX (US);
Frank K. Baker, Jr., Austin, TX (US);
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 27/092 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 27/11546 (2013.01); H01L 27/11573 (2013.01); H01L 29/16 (2013.01); H01L 29/42344 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/511 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells () prior to the formation of high-k metal gate electrodes for CMOS transistors () using a planarized dielectric layer () and protective mask () to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.