The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Dec. 03, 2014
Applicant:

Cirrus Logic, Inc., Austin, TX (US);

Inventors:

Marc L. Tarabbia, Austin, TX (US);

Shanjen Pan, Austin, TX (US);

Assignee:

CIRRUS LOGIC, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0682 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01);
Abstract

Trenches may be formed in layers on a semiconductor substrate for defining electrical components for an electronic device, such as an amplifier. A polishing step may be performed after formation of the trenches and deposition of other layer(s) to define regions for resistors, capacitors, or other elements in a metal layer on a semiconductor substrate. The polishing step may create discontinuities in metal layers on the semiconductor substrate that define electrically isolated regions corresponding to the resistors, capacitor, and other components of the electronic device.


Find Patent Forward Citations

Tarabbia, Marc. (2016). Formation of electrical components on a semiconductor substrate by polishing to isolate the components (U.S. Patent No. 9275992). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9275992

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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