Apparatus and method for non-intrusive random memory failure emulation within an integrated circuit

Abstract

The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.