The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Mar. 14, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Tae-Sun Kim, Seongnam-Si, KR;

Kyoung-Mook Lim, Hwaseong-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); G11C 5/02 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 5/025 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 23/3128 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06136 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups.


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