The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

May. 28, 2014
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Manish Umedlal Patel, Bangalore, IN;

Dharmendra Kumar Rai, Uttar Pradesh, IN;

Mohammed Rahim Chand Seikh, Bangalore, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 15/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/02 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); G11C 15/00 (2013.01);
Abstract

A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.


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