The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Jul. 13, 2013
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Bruce Wilson, San Jose, CA (US);

Yang Han, Sunnyvale, CA (US);

Yu Kou, San Jose, CA (US);

Rui Cao, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 20/14 (2006.01); G11B 5/09 (2006.01); G11B 20/10 (2006.01);
U.S. Cl.
CPC ...
G11B 5/09 (2013.01); G11B 20/10222 (2013.01); G11B 20/10009 (2013.01); G11B 20/10046 (2013.01); G11B 20/1403 (2013.01); G11B 2220/2516 (2013.01);
Abstract

Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.


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