The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Apr. 07, 2014
Applicant:
Altera Corporation, San Jose, CA (US);
Inventors:
Renxin Xia, San Jose, CA (US);
Juju Joyce, Sunnyvale, CA (US);
Nitin Prasad, San Jose, CA (US);
Kerry Veenstra, Felton, CA (US);
Keith Duwel, San Jose, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/10 (2006.01); G06F 17/50 (2006.01); H03K 19/177 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/10 (2013.01); G06F 17/5054 (2013.01); H03K 19/1776 (2013.01);
Abstract
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.