The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Jun. 11, 2013
Applicant:

E Ink Holdings Inc., Hsinchu, TW;

Inventors:

Kuan-Yi Lin, Hsinchu, TW;

Fang-An Shu, Hsinchu, TW;

Yao-Chou Tsai, Hsinchu, TW;

Tzung-Wei Yu, Hsinchu, TW;

Assignee:

E Ink Holdings Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/786 (2013.01); H01L 29/78648 (2013.01);
Abstract

A thin film transistor (TFT) is provided, which includes a substrate, a first gate layer, an insulation layer, a first source/drain layer, a second source/drain layer, a semiconductor layer, a passivation layer and a second gate layer. The first gate layer is disposed on the substrate. The insulation layer is disposed on the first gate layer. The first source/drain layer is disposed on the insulation layer. The second source/drain layer is disposed on the insulation layer. The semiconductor layer is disposed on the insulation layer and covers the first source/drain layer and the second source/drain layer. The passivation layer is disposed on the insulation layer and covers the semiconductor layer. The second gate layer is disposed on the passivation layer and contacts the first gate layer through a via so that the two gate layers keep a same voltage level.


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