The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Jun. 03, 2015
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Jin-woo Bae, Yongin-si, KR;
Byoung-ho Kwon, Hwaseong-si, KR;
Jong-hyuk Park, Hwaseong-si, KR;
Hye-sung Park, Anyang-si, KR;
Jun-seok Lee, Suwon-si, KR;
Ki-vin Im, Seongnam-si, KR;
Hee-sook Cheon, Suwon-si, KR;
In-seak Hwang, Suwon-si, KR;
Abstract
A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.