The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Sep. 17, 2014
Applicant:

Netlist, Inc., Irvine, CA (US);

Inventors:

Chi-She Chen, Walnut, CA (US);

Jeffrey C. Solomon, Irvine, CA (US);

Scott H. Milton, Irvine, CA (US);

Jayesh Bhakta, Cerritos, CA (US);

Assignee:

NetList, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 14/00 (2006.01); G06F 11/14 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 7/10 (2006.01); G11C 29/52 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0018 (2013.01); G06F 3/0634 (2013.01); G06F 11/1072 (2013.01); G06F 11/1441 (2013.01); G06F 12/00 (2013.01); G06F 12/0246 (2013.01); G11C 7/1072 (2013.01); G11C 29/52 (2013.01); G06F 11/2015 (2013.01); G06F 2212/7201 (2013.01);
Abstract

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.


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