The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Oct. 10, 2013
Applicant:
Dolphin Integration, Meylan, FR;
Inventor:
Ilan Sever, Kfar-Vitkin, IL;
Assignee:
Dolphin Integration, , FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 29/08 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/08 (2013.01); G11C 7/106 (2013.01); G11C 7/1051 (2013.01); G11C 7/1057 (2013.01); G11C 7/1078 (2013.01); G11C 7/22 (2013.01);
Abstract
The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.