The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Feb. 06, 2012
Applicants:

Donald Felton, Cambridge, GB;

Emre Özer, Cambridge, GB;

Sachin Satish Idgunji, San Jose, CA (US);

Inventors:

Donald Felton, Cambridge, GB;

Emre Özer, Cambridge, GB;

Sachin Satish Idgunji, San Jose, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G11C 11/406 (2006.01); G06F 21/75 (2013.01); G06F 21/79 (2013.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40622 (2013.01); G06F 21/75 (2013.01); G06F 21/79 (2013.01); G11C 11/408 (2013.01); G11C 2211/4065 (2013.01);
Abstract

An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.


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