The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Aug. 06, 2014
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Santosh Kumar Sood, New Delhi, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/505 (2013.01); H03K 19/1776 (2013.01); H03K 19/17744 (2013.01);
Abstract

Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.


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