The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Jun. 29, 2013
Applicant:

Silicon Graphics International Corp., Fremont, CA (US);

Inventors:

Steven Dean, Chippewa Falls, WI (US);

David R. Collins, Eau Claire, WI (US);

Paul Kinyon, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/0635 (2013.01); G06F 11/2084 (2013.01); G06F 11/201 (2013.01); G06F 11/2002 (2013.01); G06F 11/2007 (2013.01); G06F 11/2089 (2013.01);
Abstract

A high performance computing (HPC) system includes computing blades having a first region that includes processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation and another computing processor for performing data movement and storage. Because data movement and storage are offloaded to the secondary processor, the processors for performing the computation are not interrupted to perform these tasks. A method for use in the HPC system receives instructions in the computing processors and first data in the memory. The method includes receiving second data into the memory while continuing to execute the instructions in the computing processors, without interruption. A computer program product implementing the method is also disclosed.


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