The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Feb. 28, 2014
Applicants:
Eiji Yoshikawa, Tokyo, JP;
Jyunichi Ichikawa, Tokyo, JP;
Yukihisa Yoshida, Tokyo, JP;
Inventors:
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B81B 7/00 (2006.01); H01L 21/762 (2006.01); H01L 29/16 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01); H01L 23/26 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0038 (2013.01); B81B 3/0018 (2013.01); B81C 1/00285 (2013.01); H01L 21/76259 (2013.01); H01L 23/26 (2013.01); H01L 29/16 (2013.01); H01L 2924/0002 (2013.01);
Abstract
In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer () and an active layer wafer () which are bonded together with an oxide film () therebetween, each of the support wafer () and the active layer wafer () being a silicon wafer; a cavity () formed in a bonding surface of at least one of the silicon wafers; and a gettering material () formed on a surface on a side opposite to the bonding surface.