The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Oct. 15, 2014
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventors:

Kevin P. d'Angelo, Santa Clara, CA (US);

David Alan Brown, Los Gatos, CA (US);

John Sung K. So, Fremont, CA (US);

Jan Nilsson, Sunnyvale, CA (US);

Richard K. Williams, Cupertino, CA (US);

Assignee:

Skyworks Solutions, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/12 (2006.01); G06F 1/04 (2006.01); H03K 23/00 (2006.01); G09G 5/10 (2006.01); H05B 33/08 (2006.01); G09G 3/34 (2006.01); G06F 1/22 (2006.01); G06F 13/42 (2006.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
H05B 33/0851 (2013.01); G06F 1/06 (2013.01); G06F 1/22 (2013.01); G06F 13/4291 (2013.01); G09G 3/3406 (2013.01); G09G 5/10 (2013.01); H05B 33/0803 (2013.01); H05B 33/0815 (2013.01); G06F 1/04 (2013.01); G06F 1/12 (2013.01);
Abstract

A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.


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