The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Oct. 14, 2014
Applicant:

Olympus Corporation, Tokyo, JP;

Inventors:

Shigetoshi Sugawa, Miyagi, JP;

Nana Akahane, Tokyo, JP;

Satoru Adachi, Ibaraki, JP;

Assignees:

Tohoku University, Miyagi, JP;

OLYMPUS CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/217 (2011.01); H04N 3/14 (2006.01); H04N 5/335 (2011.01); H04N 5/363 (2011.01); H04N 5/357 (2011.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01); H04N 5/374 (2011.01);
U.S. Cl.
CPC ...
H04N 5/363 (2013.01); H04N 5/3575 (2013.01); H04N 5/378 (2013.01); H04N 5/3742 (2013.01); H04N 5/3745 (2013.01);
Abstract

A solid-state image pickup apparatus including: two-dimensionally arrayed unit pixels, each including a PD performing optical-electrical conversion of an incident light; an FD and two output terminals provided for each of pixel groups, each including one or more unit pixels, the two output terminals being capable of outputting a noise signal and a signal-noise sum signal separately; first and second transfer lines to which the output terminals are connected in common and which are capable of holding noise signal voltage and signal-noise sum signal voltage, respectively; first switches arranged between the output terminals and the first transfer lines; second switches arranged between the output terminals and the second transfer lines; third and fourth switches provided for the transfer lines, respectively; and third and fourth transfer lines to which the transfer lines are connected in parallel via third and fourth switches, respectively.


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