The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

May. 29, 2014
Applicant:

Situne Corporation, San Jose, CA (US);

Inventors:

Yahya Tousi, San Jose, CA (US);

Vahid Mesgarpour Toosi, Los Altos, CA (US);

Assignee:

SITUNE CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/18 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/183 (2013.01); H03M 1/46 (2013.01);
Abstract

Various embodiments describe systems and methods for calibrating gain mismatches and timing errors in and between individual ADC channels of a time-interleaved ADC. In some embodiments, a calibration signal (e.g., a DC signal) can be selectively applied to each ADC channel of a time-interleaved ADC to estimate a gain mismatch of the corresponding ADC channel. The gain mismatch can then be compensated by a gain correction circuit at the digital backend of the time-interleaved ADC. In some embodiments, timing errors between ADC channels of a time-interleaved ADC can be measured by applying a time varying signal to the ADC channels of the time-interleaved ADC. The timing errors can be calibrated by applying a feedback signal to a clock phase generator of the time-interleaved ADC.


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