The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Feb. 27, 2014
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventor:

Seiichiro Kihara, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/013 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356 (2013.01); H03K 19/018507 (2013.01);
Abstract

Provided is a high-reliability level shift circuit not prone to faulty operation due to noise. A level shift circuitis provided with: first and second current control elementsandinto control terminals of which a reverse-phase input signal and an in-phase input signal are input, respectively; first and second load circuitsandwhich are connected at one end to a high-side power source terminal Vb and at the other end to each of first terminals of the first and second current control elementsand; a comparatorin which a pair of differential input terminals Np and Nn are connected separately to each of the first terminals of the first and second current control elementsand; a current generating circuitin which first and second current output terminals Na and Nb are connected to second terminals of the first and second current control elementsand, and which separately generates a current which flows through the respective first and second current control elementsand; and voltage suppressing circuitsandwhich are connected separately or commonly to the first and second current output terminals Na and Nb, respectively, and suppress voltage from rising in the first and second current output terminals Na and Nb, respectively.


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