Address fault detection circuit

Abstract

A semiconductor memory device and method of operation are provided for a multi-bank memory array () with an address fault detector circuit () connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (-) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a 'no word line select,' 'false word line select,' and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (-) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.