The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Sep. 18, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rajat Mehrotra, New Delhi, IN;

Rubin Ajit Parekhji, Bangalore, IN;

Maheedhar Jalasutram, Bangalore, IN;

Charu Shrimali, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 29/12 (2006.01); G11C 16/16 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3422 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 29/12 (2013.01); G11C 16/0483 (2013.01);
Abstract

An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value '0' if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.


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