The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Nov. 27, 2013
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Min Chul Shin, Icheon-si Gyeonggi-do, KR;
Yoon Jae Shin, Icheon-si Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 13/00 (2006.01); G11C 5/14 (2006.01); G11C 7/08 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 5/143 (2013.01); G11C 5/147 (2013.01); G11C 7/06 (2013.01); G11C 7/08 (2013.01); G11C 11/56 (2013.01); G11C 2211/563 (2013.01);
Abstract
A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode.