The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Jun. 07, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Ryoji Matsuda, Kanagawa, JP;

Motoi Ashida, Kanagawa, JP;

Yasumitsu Murai, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 11/1675 (2013.01);
Abstract

A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.


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