Rendering images to lower bits per pixel formats using reduced numbers of registers

Abstract

Methods and systems render higher bit per pixel contone images to lower bit formats using multiple registers of a SIMD processor. The rendering process uses a first register to maintain contone image values of all the pixels being simultaneously processed. A second register maintains a threshold value used during the conversion process. A third register maintains one value for the print ready format pixels (e.g., those having less bits per pixel), and a fourth register maintains the other value (e.g., 0) for the print ready format pixels. Also, a fifth register maintains the conversion error amount for all the pixels being simultaneously processed. Sixth through ninth registers maintain distributed conversion error amounts produced by the diffusing process (for different pixels being simultaneously processed); and a tenth register maintains the pixels in the print-ready format produced by the conversion for all the pixels being simultaneously processed.