The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Aug. 29, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Daniel Komaromy, Budapest, HU;

Alexander Gantman, Solana Beach, CA (US);

Brian Rosenberg, San Diego, CA (US);

Arun Balakrishnan, San Diego, CA (US);

Renwei Ge, San Diego, CA (US);

Gregory Rose, San Diego, CA (US);

Anand Palanigounder, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 12/14 (2006.01); G06F 21/52 (2013.01); G06F 21/56 (2013.01); G06F 12/08 (2006.01); G06F 21/55 (2013.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 21/52 (2013.01); G06F 11/3037 (2013.01); G06F 11/3466 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 12/14 (2013.01); G06F 21/554 (2013.01); G06F 21/566 (2013.01); G06F 12/0848 (2013.01); G06F 2212/452 (2013.01);
Abstract

Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.


Find Patent Forward Citations

Loading…