The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Apr. 07, 2015
Applicant:

Reniac, Inc., San Jose, CA (US);

Inventors:

Prasanna Sundararajan, San Jose, CA (US);

Chidamber Kulkarni, Kondapur, IN;

Assignee:

Reniac, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0862 (2013.01); G06F 12/0873 (2013.01); G06F 12/0888 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/205 (2013.01);
Abstract

A heterogeneous memory system includes a network interface card, a main memory arrangement, a first-level cache, and a memory management unit (MMU). The main memory arrangement, first-level cache and the MMU are disposed on the network interface card. The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.


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