The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Jan. 03, 2013
Applicant:

Fujitsu Semiconductor Limited, Yokohama-shi, Kanagawa, JP;

Inventors:

Hiroshi Hatano, Kawasaki, JP;

Koichi Suzuki, Yokohama, JP;

Assignee:

SOCIONEXT INC., Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 13/00 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30149 (2013.01); G06F 9/3017 (2013.01); G06F 9/30036 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3836 (2013.01); G06F 9/3873 (2013.01); G06F 9/3887 (2013.01);
Abstract

A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.


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