The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

May. 13, 2014
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Ayan Banerjee, Fremont, CA (US);

Ramesh V. N. Ponnapalli, Sunnyvale, CA (US);

Assignee:

CISCO TECHNOLOGY, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/931 (2013.01); H04L 29/12 (2006.01);
U.S. Cl.
CPC ...
H04L 49/602 (2013.01); H04L 61/251 (2013.01); H04L 61/2542 (2013.01); H04L 61/6022 (2013.01); H04L 61/6059 (2013.01); H04L 61/6086 (2013.01);
Abstract

An example method for hierarchical programming of dual-stack switches in a network environment is provided and includes receiving packets from the network at a line card in the modular switch, a first portion of the packets being destined to Internet Protocol version 6 (IPv6) destination IP (DIP) addresses and a second portion of the packets being destined to IPv4 DIP addresses, and performing hierarchical lookups of the IPv6 DIP addresses and the IPv4 DIP addresses. Layer 3 (L3) lookups for the IPv6 DIP addresses are performed at the line card, and L3 lookups for IPv4 DIP addresses are performed at a fabric module in the modular switch. The line card and the fabric module are interconnected inside a chassis of the modular switch. In specific embodiments, the method further comprises inspecting the packets' destination Media Access Control (DMAC) addresses comprising router MAC addresses indicative of IPv6 or IPv4 address families.


Find Patent Forward Citations

Banerjee, Ayan. (2016). Hierarchical programming of dual-stack switches in a network environment (U.S. Patent No. 9258255). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9258255

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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